High speed self-adjusting clock recovery circuit with frequency detection

ABSTRACT

A clock recovery circuit based upon an early-late gate approach is applied to high speed serial communication links using NRZ data. The circuit has no systematic phase offset and therefore requires no external phase adjustment circuits or mechanisms. The circuit is used in high speed integrated receivers for applications including fiber optics, disk-drive read/write electronics, mobile communications and high rate- twisted pair data transmission in multimedia systems. Quadrature samples are obtained and held which follow the shape of the NRZ data transition as a function of phase offset. The data signal is passed through the limiter giving rise to a sawtooth shaped phase error signal. A derivative of the error function is taken to provide a frequency error signal to provide for frequency detection and assistance in frequency acquisition of the phase lock loop circuit generating the recovered clock signal from a variably controlled oscillator.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to the field of clock extraction circuits used indigital communication, and in particular, to a high speed self-adjustingclock extraction circuit used with nonreturn-to-zero (NRZ) data.

2. Description of the Prior Art

Communication of information using digital methods is preferable in mostinstances to analog methods due to the immunity to interference, errorcorrecting channel coding methodologies available, time divisionmultiplexing of signals for increased channel usage, and source codingfor efficient information transfer, which is available in the digitalformat. Whenever information is transmitted digitally, it is broken intoa sequence of symbols belonging to a finite alphabet. In order toreceive these signals, the receiver must be synchronized with theincoming data such that the information can be sampled at theappropriate time.

Often there is a hierarchy of synchronization that must be performed.For example, in a video system, a receiver must recognize individualbits. Therefore, a clock in a video system must exist at the bit rate toprovide bit level synchronization. Bits are ordered into larger groups,called bytes, which in turn are reordered into even still larger groupsdesignated as lines, which in turn are organized into larger groupsstill defined as frames. For video operation, a receiver must know whenthe beginning of each frame occurs. Usually, synchronization at theframe and line levels is determined by software and system protocols.However, at the lowest level, bit synchronization must occur, otherwisethere will be no intelligible information available to make softwarecontrolled decisions at higher levels.

A common modulation format for digital data is the nonreturn to zero(NRZ) format, which is also known on-off keying because the signal is onfor one binary state, and off for the other. The binary NRZ signal makestransitions from one binary state to the other only when there is achange in the bit value. For example, the signal 111 in NRZ format willbe an unbroken high logic level for three bit intervals. If the signalshould then become 1110, a negative transition will occur after threebit intervals and a single bit interval will be at the low logic levelwhere the signal will remain until a logical 1 is again to berepresented.

The advantages of NRZ format is that is does not occupy as muchbandwidth as other digital formatting schemes, such as return-to-zero(RZ) or Manchester coding. Further, about 90 percent of the signalenergy of NRZ data is contained within the bit rate frequency, B_(T),and about 80 percent of the energy lies within a frequency of B_(T/2).convenient way to picture random digital data is to superimpose sectionsof the digital signal separated by integer multiples of the bit periodT. Such a plot is called an "eye diagram" and illustrates the structureinherent in random data. FIG. 1 is a block diagram of a typical priorart fiber optic receiver, generally denoted by reference numeral 10,associated with eye diagrams of the data and clock signals at variousnodes within the circuit. For example, the eye diagram of FIG. 2a is theinput data signal provided at input 10 to preamplifier 14. Thedispersion of the optical fiber typically band limits the data,therefore, the square wave NRZ data is modeled in this example as havingsinusoidal transitions between the high and low logic states. The inputsignal is shown without noise and is very weak so that it must beamplified by preamplifier 14, where it is unavoidably corrupted by noiseso that the form at output 16 appears as shown in the eye diagram ofFIG. 2b. The noise of the preamplifier generally determines the overallsignal-to-noise ratio of the receiver, as the input signal is weakest atinput 12 of receiver circuit 10.

The signal is again amplified by a post-amplifier 18, which performsnoise filtering and has an automatic gain control function to keep theinput of the clock recovering decision circuit following it at a fixedlevel. Average power circuit 30 is used in the automatic gain control.FIG. 2c is an eye diagram of the filtered data and recovered clocksignal at output 20 of post-amplifier 18. Note that the recovered clocksignal undergoes a positive transition 22 at the center of each bitinterval. A decision circuit 24 compares the received data with the zerovoltage level on every positive zero crossing of 22 of the clock andmakes a decision as to the polarity of the bit. This process is known asretiming the data because the weak input signal is cleaned, regeneratedand synchronized or retimed to a local clocks The eye diagram of theretimed data and recovered clock are then provided at output 26 ofdecision circuit 24 as shown in the eye diagram of FIG. 2d. The clocksignal is extracted from output 20 by a clock extraction circuit 28 andreinserted into decision circuit 24 for retiming the data. Ademultiplexer 32 is coupled to output 26, typically to demultiplexinterleaved multiple digital signals transmitted in the fiber opticthrough circuit 10.

Clearly, recovering a clock signal from random data is crucial to theerror-free operation of any receiver circuit. The decision circuit mustalso sample data at an appropriate time, otherwise its performance willdegrade. Because the input data is random, there will be random phasereversals in the data which eliminate any strong spectral component inthe data input stream. In fact, there is a spectral null at integermultiples of the bit rate in NRZ formatted data. Therefore, in order toextract a clock from random NRZ data, nonlinear processing of the datasignal must be occur. Typically the nonlinear operation is based on someform of edge detection, which generates a pulse whenever the data makesa positive or negative transition. Such a detection effectively convertsan NRZ data stream into a return to zero (RZ) data stream, which doeshave a strong spectral component at the bit rate. Once the RZ signal isproduced, the clock can be extracted by various means.

Prior art clock extraction circuits from NRZ data can be classified intwo main categories: (a) open loop filters; and (b) closed loopedsynchronizers. Heretofore, open loop filters have almost exclusivelybeen used in high bit rate receivers. In an open loop technique, theperiodic tiring information is extracted from the data by first using anonlinear edge enhancement circuit to generate a spectral line at thebit rate. A signal is then passed through a narrow band filter centeredat the bit rate frequency. Typically, surface-acoustic-wave (SAW)filters have been used for this purpose, though commercial embodimentshave generally operated at 3 GHz or less. See for example Z. Wang etal., "Multi Gigabit per Second Silicon Bipolar Clock Recovery IC OpticalReceivers,"IEEE J. Select. Areas Commum Volume SAC-9, pages 256-63 (June1991).

The open loop technique suffers from instabilities and nonlinearproblems, such as frequency acquisition and cycle slipping. Further,open loop systems usually need to be manually adjusted to center theclock edge in the bit interval. A one-time manual adjustment clearlydoes not track phase offsets due to temperature variations and componentaging. The filter in the open looped circuit is also generally externalto the receiver electronics and is bulky, leading to both packaging andinterconnection problems.

The closed looped synchronizer is integratable and can continuallycompensate for changes in the environment and input bit rate. The closedloop system requires a voltage control oscillator (VCO) to be tuned by asuitably filtered error signal in order to align the transitions of theclock to the center of the bit interval. Although a closed loopsynchronizer has the ability to be able to track changes in phase andfrequency of the data signal, complications arise due to nonlinearfrequency acquisition and tracking which makes the circuit difficult todesign Clock recovery circuits presently limit the obtainable data rateof multigigabit per second integrated fiber optic receivers.

Currently, practical receivers that include methods of extracting theclock signal from the data are limited to about 25 gigabits per secondfor open loop systems using a SAW filter for clock extraction such asshown by B. Wedding et al, "2.24 Gigabit Per Second 151-KilometerOptical Transmission System Using High Speed Integrated SiliconCircuits," IEEE J. Select. Areas Commun.., Vol. SAC-8, pages 227-34(February 1990), and for closed loop synchronizing systems using a phaselock loop such as shown by H. Ransin et al., "A 2.5 Gigabit Per SecondGallium Arsenide Clock and Data Regenerator IC," IEEE Gallium ArsenideIC Symposium, New Orleans, La., Pages 57-60 (October 1990). Manypractitioners have been working in the art to produce a 10 gigabit persecond integrated fiber optic receiver, but the main stumbling block hasbeen the clock recovery circuit. The clock recovery loop measures theclock-phase and aligns it to minimize the bit error rate. There arenotable differences in delays between the edge detection circuit and thedecision circuit that result in a steady state phase offset that must becompensated by an additional phase adjustment. Unfortunately, thisadditional phase adjustment is outside the negative feedback loop and,thus, is typically provided manually via external components.

What is needed then is a design which can be fully integrated withoutexternal delay lines used for tuning and which will provide automaticoptimal phase alignment of a clock recovery circuit on chip. Theintegrated design must be a self-correcting clock which includes thedecision circuit in the feedback loop for final clock-phase adjustments.

Brief Summary of the Invention

The invention is a clock recovery circuit for establishing bitsynchronization with an NRZ data formatted bit stream. The circuitcomprises a matched filter for receiving the NRZ bit stream forproducing a filtered output signal indicative of edge transitions in thebit stream. A first and second sample and hold circuit have inputscoupled to the matched filter. For the purpose of this specification asample and hold circuit shall be defined to include any circuit whichperforms an equivalent function to a sample and hold circuit, such as atracking and hold circuit. The sample and hold circuits arecomplementarily clocked by a VCO signal. The first sample and holdcircuit holds in-phase samples and the second sample and hold secondholds quadrature samples. A third sample and hold circuit having aninput coupled to the second sample and hold circuit. The third sampleand hold circuit is clocked on positive and negative transitions of adata output signal generated from the first sample and hold circuit. Amultiplier multiplies or corrects the sign of the quadrature samplesignal output from the third sample and hold circuit. A lowpass filteris coupled to the multiplier and filters output of the multiplier toobtain a DC value of phase error between the data output signal and thequadrature sample or what can be thought of as the data crossoversample. A variable controlled oscillator (VCO) has its control inputcoupled to the filter. The variable controlled oscillator generates theVCO signal with a controllable phase according to the DC value providedby the filter. The VCO is coupled to the first and second sample andhold circuits to complementarily clock the first and second sample andhold circuits. As a result, a data transition tracking loop is providedwhich is high speed, inherently self-adjusting, is independent of datatransition density with significantly reduced ripple in the error signalgenerated by the multiplier.

The circuit further comprises a limiter coupled to the output of thefirst sample and hold circuit. The limiter has its output coupled to themultiplier so that output of the multiplier, which is representative ofphase error, is monotonic across the phase error signal centered on abit interval. The output of the limiter is the data output signal. Thephase error signal output by the multiplier is a sawtooth wave form.

The circuit further comprising another limiter coupled to the VCO signalof the VCO for generating a clock signal indicative of a recapturedclock from the data bit stream.

Another embodiment of the circuit further comprising a frequency lockdetector for providing a frequency error signal to the VCO. The VCO isresponsive to the frequency error signal to shift frequency of the VCOin alignment with bit rate frequency of the data stream prior to phaselock The frequency lock detector is enabled only when absolute value ofphase error exceeds a predetermined threshold.

In still another embodiment the circuit is arranged and configured tooperate in a bit interleaved fashion so that the first and second sampleand hold circuits each comprise a pair of complementarily clockedtracking and hold circuits having their input coupled to the matchedfilter and a multiplexer having its inputs coupled to outputs of thepair of tracking and hold circuits. The tracking and hold circuits arecomplementarily clocked by selected outputs from the VCO. The VCO has alead output, Q, and an lag output, I. The tracking and hold circuits ofthe first sample and hold circuit are clocked by the lag output from theVCO while the pair of tracking and hold circuits of the second sampleand hold circuit are clocked by the lead output from the VCO.

The third sample and hold circuit comprises a pair of complementarilyclocked tracking and hold circuits complementarily clocked by the dataoutput signal and having their input coupled to an output of themultiplexer included within the second sample and hold circuit whichgenerates data cross-over samples. A multiplexer is coupled to outputsfrom the pair of tracking and hold circuits included in the third sampleand hold circuit. The multiplexer of the third sample and hold circuithas an output coupled to the filter. An inverter is coupled between anoutput of one of the tracking and hold circuits and an input of themultiplexer to invert tracked and held data cross-over samples when thetracking and hold circuit coupled thereto is clocked by a negativetransition of the data output signal.

The tracking and hold circuits and multiplexers comprising the first,second, and third sample and hold circuits are matched throughsubstantially identical integrated circuit fabrication to inherentlynull out systematic phase errors within the circuit.

The frequency lock detector comprises a fourth sample and hold circuitcomprised of a pair of tracking and hold circuits complementarilyclocked by the data output signal each having their inputs coupled tothe lowpass filter. A multiplexer has its inputs coupled to outputs ofthe pair of tracking and hold circuits of the fourth sample and holdcircuit. A second lowpass filter has its input coupled to an output ofthe multiplexer of the fourth sample and hold circuit. A summing node iscoupled to the second lowpass filter for differencing with the phaseerror signal. A limiter has its input coupled to the summing node togenerate a frequency error signal.

The circuit further comprises a lock detect gate for breaking connectionbetween the limiter and the lowpass filter when absolute value of thephase error signal is below a predetermined threshold, so that the VCOis controlled only by the phase error below the threshold and by thefrequency error above the threshold.

The invention is also a method of recovering a clock signal from an NRZdata bit stream comprising the steps of detecting edge transitions ofthe NRZ data bit stream. A quadrature sample signal is generatedcorresponding to the NRZ data bit stream. The quadrature signal isselectively passed to a phase detector output. The quadrature samplesignal is passed to the phase detector output if the NRZ data makes alow to high transition. A negative of the quadrature sample signal ispassed to the phase detector output if the NRZ data signal makes a highto low transition. Otherwise if the NRZ data signal makes no transition,a previous phase error value is held in the phase detector output. Avariably controlled oscillator (VCO) is then controlled according to thephase detector output. A recaptured clock signal is generated by thecontrolled VCO. As a result, the clock signal is recovered in aself-adjusting circuit with no steady state phase error, ripple inducedphase jitter is substantially eliminated, and phase error output isindependent of data density and high speed operation is enabled.

The method further comprising the step of generating from the output ofthe phase error detector a frequency error signal. The frequency errorsignal is selectively combined with output of the phase detector tocontrol frequency of the VCO to thereby frequency lock to the NRZ databit stream.

The method further comprising the step of generating a monotonicallyincreasing phase error signal extending across a bit interval centeredon zero phase error in the form of a sawtooth wave form for controllingthe VCO.

The method further comprises the step of generating from the output ofthe phase error detector a frequency error signal. The frequency errorsignal is selectively combined with output of the phase detector tocontrol frequency of the VCO to thereby frequency lock to the NRZ databit stream.

Finally, the invention can be characterized as a circuit for recapturinga clock signal from an NRZ data bit stream comprising a clocked sampleand hold circuit for sampling and holding an in-phase sample signal ofthe NRZ data bit stream. A clocked sample and hold circuit is alsoprovided for sampling and holding a quadrature sample signal of the NRZdata bit stream. A phase detector circuit selectively passes thequadrature sample signal to a phase detector output The quadraturesample signal is passed to the phase detector output if the NRZ datamakes a low to high transition. The negative of the quadrature samplesignal is passed to the phase detector output if the NRZ data makes ahigh to low transition. The previously passed quadrature sample signalis held at the phase detector output if the NRZ data makes notransition. A variable controlled oscillator circuit receives the phasedetector output and responsively generates an in-phase clock signal. Theclocked sample and hold circuit for sampling and holding an in-phasesample signal of the NRZ data bit stream and the clocked sample and holdcircuit for sampling and holding a quadrature sample signal of the NRZdata bit stream are complementarily clocked by the in-phase clocksignal.

The invention and its various embodiments may be better visualized bynow turning to the following drawings wherein like elements arereferenced by like numerals.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a prior art fiber optic receiver.

FIGS. 2a-2d are eye diagrams of a random data and recovered clock signalat various nodes within the circuit of FIG. 1.

FIG. 3 is a functional block diagram of a circuit incorporating theinvention.

FIG. 4 is a functional block diagram of the circuit of FIG. 3 which hasbeen modified to include a frequency detector and frequency lock loop.

FIG. 5 is a is a functional block diagram of a prior art circuit showingan early-late gate clock recovery circuit design

FIG. 6 is a is a functional block diagram of a prior art circuit whichis a modification of the circuit of FIG. 5 in which the time delay isequal to the bit interval.

FIG. 7 is a modification of an early-late clock recovery circuit whichhas been modified according to the invention.

FIG. 8 is a simplified timing diagram showing a typical NRZ data streamand its corresponding matched filter output as used in the circuit ofFIG. 7.

FIGS. 9a-c are simplified timing diagrams which illustrate therelationship of quadrature sample signals to early, on-time and latein-phase sample and which illustrates that the gradient or slope of theon-time sample is equal to the value of the crossover sample.

FIG. 10 is a functional block diagram of a digital transition trackingloop (DTTL) of the invention.

FIG. 11 is a timing diagram showing the form of the phase error signalproduced in FIG. 10.

FIGS. 12a and 12b are simplified timing diagrams showing the phase errorsignal and its derivative as a function of time for a slow and fastclock respectively.

FIG. 13 is a functional block diagram of a circuit for extracting afrequency error signal from a sawtooth phase error signal.

FIGS. 14a and 14b are simplified timing diagrams which show frequencyerror polarity extraction from a sawtooth phase error signal for a slowand fast clock respectively.

FIG. 15 is a graph illustrating dead-zone control for the generation ofa frequency error signal.

FIG. 16 is a functional block diagram of a circuit for implementing thedeadzone control shown in FIG. 15.

The invention and its various embodiments may now be understood byturning to the following detailed description.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The invention is a clock recovery or extraction circuit. EI theillustrated embodiment, the circuit is used to extract a clock signalfrom random, nonreturn-to-zero (NRZ) data The general field ofapplication for the circuit is in digital communications and is expectedto be particularly useful for high speed, broad band modulation formats,although its use is not restricted to such schemes. A functional blockdiagram of the illustrated embodiment of the invention is shown anddescribed in connection with FIG. 3. A second embodiment in a modifiedcircuit is shown in the block diagram of FIG. 4. The clock recoverycircuit of FIGS. 3 and 4 is designed such that the residual phase-errorsbetween the data signal and the extracted clock signal are minimized.This is accomplished in two ways. First, a negative feedback loop isused to phase lock the extracted the clock to the time varyingdeviations of the data signal. Second, any residual offsets in thesteady state phase error are nulled out by using identical and matching,circuit building blocks in the phase detector.

The clock extraction circuit can also detect frequency differencesbetween the data and the clock signal. This ability to detect frequencydifferences is used for acquiring an additional phase lock. Thefrequency error signal is used to drive the clock signal to the correctfrequency so that an initial phase lock can occur at start up.

The circuit is capable of performing at very high speeds and isinherently self-adjusting. As stated, it can detect frequency errors toassist in acquisition of initial phase lock. The phase detector functionis monotonic over the bit interval thereby improving phase tracking andfrequency acquisition. Ripple induced phase jitter is significantlyreduced by resampling the phase error only after a data transition. Thephase error is independent of the transition density thereby eliminatingdata pattern dependent jitter. The sensitivity of the circuit isimproved by using sample and hold circuits before the decision circuit.

It is expressly contemplated that the circuit will be of utility infiber optic data links, disk drive read/write electronics, local areanetworks, and wireless communications. These areas are expected to seekcontinued growth in the future due to a demand for low cost, low powerinterconnection of computer networks, mobile data links, and multimediaservices, such as video-on-demand, home shopping, home banking,interactive educational programs, and the like.

Before the digital transition tracking loop (DTTL) of the invention isdescribed in connection with FIGS. 3 and 4, it will be helpful to reviewsome background concerning conventional designs with respect toearly-late clock recovery circuits. In these circuits, data is detectedusing an early clock, a late clock, and an on time clock. By subtractingthe late from the early clock signal, and multiplying the retimed datato remove polarity variations or unwanted changes in sign, a phase errorsignal is derived, which will go to zero when the early and late clocksare exactly centered at about the optimal sampling point. FIG. 5 is afunctional block diagram of a conventional early-late gate clockrecovery circuit using rectifiers in each arm of the circuit. Thecircuit is well known and discussions of its performance can be found,for example, in Gardner, "Phase Lock Techniques," New York, Wiley, 2dEd. 1979, at page 235.

If the time delay of the late sample of the current bit is equal to thebit period, then the late sample will occur at exactly the same time asthe early sample of the following bit. Therefore, the early timingresult can be obtained by delaying the late correlator output, thus,eliminating the early correlator from the circuit of FIG. 5. Based onthis assumption, the circuit of FIG. 5 has been simplified to thefunctional block diagram shown in FIG. 6. This circuit has beendescribed by Stiffier, "Theory of Synchronous Communications," InglewoodCliffs, N.J., Prentice Hall Inc. 1971 at page 227.

The speed of the circuit of FIG. 6 is limited by the need to perform theintegrate and dump functions. However, by replacing the correlators ofthe circuit of FIG. 6 with a matched filter, a circuit is derived whichcan be used at high speeds. The functional block diagram of this circuitis shown in FIG. 7. The difficulty with a practical limitation of acircuit describe in FIG. 7 is that some type of assistance is requiredin frequency acquisition for the initial phase lock. Without this typeof assistance, the VCO center frequency of the circuit of FIG. 7 must bestable within 0.1 percent over all processing and temperaturevariations, which is difficult to meet in practical applications.

It is an inherent feature of NRZ data formatting that timing informationfor NRZ data is only present when the data make a transition. Therefore,the output of the phase detector between bit intervals can be ignoredwhen no data transition occurs in the bit interval. The phase detectormay thereby be shut off by a gating mechanism in absence of datatransitions. The modified early-late gate of the invention adds anadditional sampling stage to transfer the phase-detector output to theloop filter only when a data transition has occurred. A similar approachwas used in an application for clock phase estimates at very low speedsby Paine et al, "Transition Tracking Bit Synchronization System," U.S.Pat. No. 3,626,298 (1971).

The data transition tracking loop of the invention can best beunderstood by considering its operation in the time domain. FIG. 8 showsa typical rectangular NRZ data pattern on line 34 before and on line 36after being passed through a matched filter. The matched filter producesa linear transition shown on line 36 that extends over one bit interval.Positive going data transitions produce a linear positive slope andnegative going data transitions produce a linear negative slope over onebit interval. Since we are only interested in what happens during datatransitions, consider first the positive data pulse 38 shown on line 36in FIG. 8. Recall that the ultimate goal is to position the phase of therecovered clock so that the sample is taken at the point where thefiltered data signal achieves a maximum signal-to-noise ratio. As itturns out, we would like to find the gradient of the on-time samples andforce this value to zero. In the case of high speed data communicationsystems, several parasitic poles near the data rate provide additionalfiltering of the data. The result is that the data transitions follownearly a sinusoidal path and for a data pattern of alternately ones andzeros, the data signal is a sine wave at half the bit rate.

For this special case of sinusoidal transitions, the gradient or slopeof the on-time samples can be found by shifting the sampling phase halfa bit period. Positive data pulse 38 is characterized by a datacrossover sampling point 40 and an optimal sampling point 42. Thisspecial case is illustrated in FIGS. 9a-c. The phase-shifted samplepoint or the quadrature sample, which is shifted forward by one quarterof a clock interval (half the bit interval), is shown in the case of anearly clock in FIG. 9a, indicating that the quadrature sample isnegative; shown for an on-time clock in FIG. 9b indicating thequadrature sample is zero; and in the case of a late clock, in FIG. 9c,indicating that the quadrature is positive, which is also equal to thederivative or gradient of the curve at the in-phase sample point. Theopposite condition can be considered when the data pulse is negativesuch as shown for pulse 44 in FIG. 8, in which case the plurality of thequadrature samples are reversed from those shown in FIGS. 9a-9c. Thesign or polarity reversal is removed by multiplying the quadraturesamples by the retimed data, if the data is treated as taking the values(1, -1), which is typically the case for NRZ data.

Since the quadrature samples values are transferred to the loop filteronly when the data transition occurs, we can obtain the following simplelist of rules for obtaining the desired phase error signal.

a If the data makes a low to high transition, pass the quadrature sampleto the phase detector output.

b. If the data makes a high to low transition, pass the negative of thequadrature sample to the phase detector output.

c. If the data makes no transition, hold the previous phase error value.

The circuits shown in functional block diagram of FIG. 10 implementsthese rules. It can be seen from this circuit that the quadraturesamples follow the data transitions as a function of the phase-offset.The input data is coupled to a matched filter 46 which outputs the datatransitions edges. The output of matched filter 46 is coupled to twocomplementarily clocked sample and hold circuits 48 and 50. Sample andhold circuit 48 is in the in-phase sample arm and is clocked on thepositive data transitions. Its output is coupled to a limiter 52.Limiter 52 cleans up the noise from sample and hold circuit 48 andoutputs unambiguous high and low logic signals (1, -1). The output oflimiter 52 is the data output, is also fed back both to a multiplier 54for polarity correction of the phase error signal as discussed above,and is used as the clock input of sample and hold circuit 56. Thequadrature samples are taken by sample and hold 50 on the negativetransition of the clock or what would be considered the cross-over pointfor an on-time signal. The cross-over samples thus contains the phaseerror information as was illustrated in FIGS. 9a-c. The phase errorinformation is valid, however, only when a data transition occurs andthe polarity of the quadrature signal switches with the data value.

Therefore, the quadrature sample is processed by means of sample andhold circuit 56, which has its input coupled to the output of sample andhold circuit 50. Sample and hold circuit 56 is devised such that itsamples on both positive and negative data transitions. As a result, allquadrature samples that are taken by sample and hold circuit 50 will beignored until a data transition occurs at which time the output will bepassed to the phase lock loop after sign reversal if necessary bymultiplication by the data signal. The output of sample and hold circuit56 is coupled to the second input of multiplier 54. The output ofmultiplier 54 is the phase error signal. The phase error signal isfiltered by a low pass filter 58 whose dc output is the error correctionsignal which is coupled to VCO 60. The phase of the clock generated byVCO 60 is varied in a direction so that the phase error signal isnulled, i.e. phased locked to the true data clock signal. VCO 60generates the clock for sample and hold circuits 48 and 50 and drivesclock output limiter 62 to produce the recovered clock signal Becausethe data signals pass through limiter 52 before multiplying thequadrature samples in multiplier 54, the plurality of the signal changesabruptly at a cycle-slip boundary, giving rise to a sawtooth-type phasedetector characteristic illustrated in the timing graph of FIG. 11. Theboundary at which cycle slipping might occur is defined as thecycle-slip boundary. It is the place in the data stream, where forexample, synchronization might be suddenly lost and then reacquired, butonly at an integer number of bit interval later with the possible lossof the interlying bits.

FIG. 11 shows the phase error signal at the output of multiplier 54 as afunction of the time offsets between the data transitions and the clocksignal from VCO 60. The sawtooth curve 64 clearly illustrates that thephase detector is monotonic over the entire bit interval -T/2, T/2! sothat the phase error signal follows the shape of the data transitionuntil it abruptly changes sign at the time when the offsets equal toone-half the bit interval.

In a practical implementation in the circuit in FIG. 11, a bitinterleaved data transition tracking loop is preferably used as shown inFIG. 3. As is the general practice in this specification, substantiallysimilar elements described in connection with FIG. 10 are referencedwith the same reference numerals in FIG. 3. The data again is input intoa matched filter 46 and coupled to complementarily clocked track andhold circuits 64, 66, 68 and 70. A sample and hold can only change itsvalue when the clock changes. Therefore you get a staircase type ofoutput from a sample and hold circuit. A single circuit implementationof a sample and hold is difficult to make. A track and hold circuit hastwo phases: 1) in the first phase it tracks the signal with unity gain;and 2) in the second phase it holds the value that was present at theclock edge. A track and hold circuit can be built in a straight forwardway. A sample-and-hold function can be reproduced with twotrack-and-hold circuits and a multiplexor. In this way, onetrack-and-hold circuit is tracking while the other track-and-holdcircuit is holding and vica versa.

In the present invention two separate track and hold circuits are usedto interleave data and to speed up the circuit operation. The onlycircuit that has to ran at full speed are the multiplexers, which aretypically the fastest circuits. The circuit speed is limited then onlyby one of the fastest types of circuits employed.

The output of track and hold circuits 64-70 are then coupled throughcorresponding multiplexers 72 and 74. Multiplexer 72 corresponds totrack and hold circuit 64 and 66, while multiplexer 74 corresponds totrack and hold circuit 68 and 70. The output of multiplexer 74 is thencoupled through a buffer circuit 76 to track and hold circuits 78 and80. The purpose of buffer circuit 76 is to insert a circuit delay togenerally match the delay inserted by limiter 52 to the data outputsignal, so that the quadrature sample input to track and hold circuits78 and 80 is more or less still time correlated to the data outputsignal used as the complementary clock signal for track and holdcircuits 78 and 80.

The output of track and hold circuit 80 is inverted by inverter 82 tocorrect polarity reversal since track and hold circuit 80 is clocked onthe negative data transition. The output of inverter 82 is coupled to amultiplexer 84 whose other input is coupled to the output of track andhold circuit 78. The output of multiplexer 84 is the phase error signal,coupled as before in the case of FIG. 10 to lowpass filter 58 and thenceto VCO 61.

The output of VCO 61 is the clock signal to track and hold circuits64-70 and is provided through limiter 62 as the recovered clock signal.The output data is coupled from multiplexer 72 through limiter 52 andprovided as an output at node 86. The output data is used as the clocksignal for multiplexer 84. Multiplexers 72 and 74 are clocked by VCO 61.The I and Q outputs from VCO 61 are 90 degrees out of phase with eachother and are separated in time by a half a bit interval, T/2, since VCO61 generates a clock signal at half the bit rate. I is in phase with thetrue data clock rate when the phase error is nulled, while Q leads I byan interval of T/2.

VCO 61 operates at a center frequency which is half the data bit rate.The output of VCO 61 is a quadrature output for sampling the data at thedata crossover points. The multiplexed track and hold circuits 64-70perform the function of the sample and hold circuits of FIG. 10 on a bitinterleaved basis to sample and hold the data on both positive andnegative going clock transitions in the same manner as described inconnection with the circuit of FIG. 10. Track and hold circuits 78 and80 with multiplexer 84 and inverter 82 perform in an bit interleavedmanner substantially the same function as sample and hold circuit 56,and multiplier 54 of the circuit of FIG. 10.

Track and hold circuits 64 and 66, together with multiplexer 72,comprises a repeatable structure. Although the resampling circuit, trackand hold circuits 78 and 80 with multiplexer 84, has a reverse ofpolarity for a negative data transition, in for example a fullydifferential circuit, this is easily realized by switching the polarityof the differential signals. Thus, the layout of the resampling circuitis identical to the front end of the circuit except for a crossover inthe wiring. This allows the three sets of track and hold circuits andmultiplexer to be fabricated as substantially matched circuit groupingsin an integrated circuit.

The phase detector of FIG. 3 operates at very high speeds and since thephase detector and decision portion use identically fabricatedintegrated circuitry, the sampling phase is inherently self-adjusting.The circuit samples at half the data bit time width, T/2 seconds, offsetfrom the data crossovers. Although this sample point may not be optimalfor sinusoidal pulse shapes, for any other pulse shape it achieves amaximum signal-to-noise ratio at the center of the bit interval which isthe optimum sampling point.

Since the signal is sampled and held before a decision is made as towhether it is a high or low logic value, the regeneration of the datadoes not interfere with the data acquisition. Therefore, thesignal-to-noise ratio is not adversely effected. In other circuitdesigns when flip-flops are used to sample and regenerate the datainstead of a track and hold circuit, the effect of regeneration on thedata sampling makes it unclear as to where the optimum sampling pointoccurs and thus may not be in the center of the bit interval. Thissampling uncertainty reduces receiver sensitivity in those other casesand the present invention is immune from this type of defect A decisioncircuit must do three things:

1) sample

2) determine whether result of sample is high or low

3) regenerate or latch this result to a stable noiseless voltage level

In the present design these operations are separated so access to eachintermediate result is possible. Circuits that use a flip-flop getretimed or regenerated data output. However, it's not clear at all wherethe decision was made as to the proper polarity of the sample, andwhether the sample was taken at the right time. The circuit of theinvention uses interleaving to increase throughput. How it does this isdifferent, however, from other interleaved circuits because of thesampling operation. In other circuits a D-type flip-flop is used assampler decision-circuit, and regenerator. These three basic functionscan interfere with each other, especially when the clock edge is slowcompared to the bit period. The result is that a D-type flip-flop mustbe quick even if it's interleaved because the input signal is stillmoving fast even though the clock period is reduced. Thereforeinterleaving will not actually buy you an increase in speed. In circuitof the invention the limiting element in speed is the track and holdcircuit and the multiplexor. But this takes the decision function andregeneration out of the critical path and allows twice the time toperform this function. In the circuit of the invention the sample isalso held steady for two bit periods so the latch or regenerationcircuit has plenty of time to reach the desired voltage.

The data decision is made after the multiplexor in limiter 52. Becausethe signal is sampled and held, it is not necessary to have a latch orregenerator to make sure that the bit won't change in the middle of abit interval. If desired latching can be added after the limiter tofurther square-up the data-output.

It is contemplated that in a very high-speed system to take advantage ofinterleaving the decisions will be made in parallel. Therefore aseparate path will be provided for each track-and-hold with a limiterand regenerator.

The circuits of FIGS. 3 and 10 have a phase detector output which ismonotonic over the bit interval The output is independent of the datatransition-density to a first order thereby substantially reducing datapattern dependent jitter in the recovered clock. Resampling the phaseerror signal at data transitions significantly reduces ripple in theerror signal and thereby reduces phase jitter in the recovered clocksignal.

The circuit can also be viewed as a modification of a gradient basedmaximum a posterior (MAP) estimator. See generally Buchwald, "Design ofIntegrated Fiber Optic Receivers Using Hetero Junction BipolarTransistors," Ph.D. Thesis, University of California, Los Angeles,(January 1993). Assume that you have a parameter, t, that you want toestimate, and

a signal that you are observing y(.). There are two probabilities thatare significant for this estimation. We could consider a case where thetime offset it by t and we want to find the likelihood that we receiveda particular y from the sample space y(.). The likelihood is: Pr(y|t)defined as the likelihood.

We could design a receiver that looks at all possible values of t andfind the find the particular to that has the largest likelihood. Then wewould estimate the time offset as to. This is known as a likelihoodtest.

We actually want to turn this around, because what we really want toknow is the probability that we have a given offset t for a specificvalue of the received signal y from the sample space y(.). This is knownas an a posterior probability and is given by:

Pr(t|y) defined as the A Posterior.

The receiver finds Pr(t|y) for all possible values of t and picks thevalue t_(o) which maximizes the A Posterior probability. This isfundamentally different from a likelihood receiver.

However, in the case of a binary system where ones are equally likely tobe transmitted as zeros, a MAP receiver and an likelihood receiver arethe same thing. In the general case the MAP is more desirable.

The illustrated circuit produces a MAP estimate under nominal operatingconditions. It can be shown that an optimal MAP receiver is one thatfind Pr(t|y) for all values of t and the picks the t_(o) with thehighest probability. It can be shown for additive Gaussian white noisethat maximizing Pr(t|y) is the same as maximizing a correlation of thesignal with a delayed copy of itself. The idea is to take the originaldata and correlate that with what was received. Then shift the timeslightly and do it again. Repeat this for all values of t. When the databits line up, the correlation will be minimum. So the value of t_(o) forthis case will be the MAP estimate of the time delay.

The problem with a system that does this is that it is not practical. Itimplies perfect analog memory and several parallel correlations. Abetter way to do this operation is to look at the output of thecorrelator as a function of the time offset. At t_(o) this function willbe a maximum Therefore the receiver looks for the maximum value of thisfunction. We can find the maximum value by taking the slope and findingwhen that slope is equal to zero. Therefore we have an alternative wayto make the receiver. We don't need to perform the correlations, we onlyneed to find the slope of the optimal correlation receiver. We then makea feedback system that drives this slope to be equal to zero. Then weknow that we have found the time offset that maximizes the correlationbetween received bits with copies of the noiseless original data.

The illustrated circuit produces a phase error that is the gradient ofthe optimal correlation function. Therefore, if used in a feedbacksystem to drive the gradient to zero, the resulting clock signal willoccur at a time that is the optimal MAP estimate of data arrival time.

For sinusoidally shaped data transitions, the use of quadrature samplesgives the gradient of the optimal correlation. Therefore, the datatransition tracking loop provides a MAP clock-phase estimate in steadystate operation, provided there is no systematic offset. However, sincethe systematic offsets are typically the dominant factors responsiblefor performance degradation of high speed circuits, the primaryadvantage of these sampled data transition tracking loop is itssymmetry, which makes the circuit insensitive to systematic errors. Theresidual phase-error in recovered clock signal will be a result only ofrandom mismatches in the circuits, which can be reduced or controlled toa high degree of accuracy in an integrated fabrication process.

Consider now frequency detection in the data transition tracking loop ofthe invention. Notwithstanding the foregoing described advantages, thecircuit of FIG. 3 might not be able to lock in to a data signal that hasa frequency which differs substantially from the VCO frequency. In factthe natural acquisition of the loop can only pull in frequency errors onthe same order of magnitude as the closed looped bandwidth. Since thecircuit has a narrow bandwidth to reduce phase jitter (high Q), thepull-in range of the circuit can be quite narrow. For example, at a datarate of 10 gigabits per second, the VCO frequency is 5 GHz. For aneffective Q of 1,000, the maximum frequency deviation which can betolerated is of the order of 10 megahertz or 0.2 percent of the VCOfrequency. It may be impractical to design a VCO with a center frequencystable to within 0.2 percent in every application.

Therefore, what is described below is the further modification of thecircuitry of FIG. 3 by the inclusion of a frequency detector to ensurefrequency acquisition will occur upon startup. Several options foraddition of a frequency detector to the circuit of FIG. 3 exists and areincluded within the scope of the invention. Any of the presently knownclock extraction circuits could be used as stand alone frequencydetectors to simply add the resulting frequency error to the phase errorof the data transition tracking loop circuit. However, since the circuitof FIG. 3 has an in-phase data samples and quadrature crossover samplesavailable to it, the preferred mode is to modify the circuitry of FIG. 3to include the function of a quadracorrelator.

A simple frequency detector can be devised once it is realized that thephase error signal is a sawtooth type function of the error. FIG. 12aillustrates the relationship between the error function and its timederivative for a clock which is too slow, while FIG. 12b illustrates thesame relationship when the clock is too fast. The derivative of theerror function is in the proper direction or has the proper polaritymost of the time. Therefore, to derive a frequency error signal thatgives only the sign of the frequency error, we need to only process thederivative by a circuit such as shown in FIG. 13. The error signal e, iscoupled to the input of a differentiator 88, whose output is coupled toa limiter 90. The frequency error, which is the output of limiter 90, isadded to the error function itself by summing circuit 92 to obtain asignal which is the sum of phase error plus frequency error. This willtransform the signal shown in FIGS. 12a and 12b, respectively, to theoutputs shown in FIGS. 14a and 14b.

The data transition tracking loop is ideal for implementing sawtoothfrequency detection because the error signal is resampled and containsvirtually no ripple.

Therefore, only a broad band low pass filter is needed to smoothglitches before producing the desired sawtooth function. The datatransition tracking loop can thus recognize frequency errors of at least10 to 20 percent to provide a significant range over which VCO centerfrequencies can vary and still be pulled in by the circuit.

Once it is understood that the slope of the sawtooth phasecharacteristic can give the direction of the frequency error, then theuse of various gating techniques and other embellishments to thefrequency detector can be incorporated to improve its performance. FIG.4 illustrates the basic structure of a practical data transitiontracking loop with frequency detection. FIG. 4 is a modification of thecircuit of FIG. 3 in which a frequency detector has been included in thefeedback path.

Considerations of closed loop stability and jitter peaking dictate thegain and transfer function of the frequency filter 58a in the frequencyerror path.

When the loop is in lock, the average frequency error will go to zero.However, it will vary randomly, and can disturb the dynamics of thephase-frequency lock loop. To reduce the effect of the frequency errorsignal on the loop when in phase lock, a lock detector can be used toforce the frequency to zero after the phase acquisition is complete. Onetechnique is the use of a dead zone near the point of zero phase error.

This is described in connection with FIG. 15. The frequency error isenabled only when the phase error exceeds a given threshold. FIG. 15 isa graph showing plus and minus time error margins within the data bitwidth in which there is a dead zone 94 such that the frequency error isnot enabled until the thresholds 96 or 98 are exceeded or reaches apoint on curve 100 out of dead zone 94.

The circuit of FIG. 16 is a functional block diagram by which thecontrol technique of FIG. 15 is implemented. The Phase error to coupledto a full wave rectifier 118 to provide the absolute value of the phaseerror. A predetermined threshold value is subtracted from the absolutevalue of the phase error in a summing node 120 with the difference beingconverted to a (0, 1) logic level by limiter 122. The output of limiter122 is coupled to multiplier 124 where it multiplies the frequency errorsignal. Because limiter 122 generates either only a 0 or a 1, multiplieracts as a dead zone switch, so that the circuit of FIG. 16 issymbolically denoted in FIG. 4 as switch 102.

With this technique, the operation of frequency acquisition can beseparated from phase tracking. During frequency acquisition, the averagephase error signal will nominally equal zero and will have no effect onthe loop. During frequency acquisition the loop will not be locked.Therefore the phase error will continually slip cycles and rotatethrough -pi, pi! in terms of clock phase or -T/2, T/2! in terms of bitperiod times. The phase will look like a linearly increasing quantityfor a constant frequency error. Therefore the output of the phasedetector with a constant frequency error will look like FIG. 11 as afunction of time. This signal has an average value of zero. It will getlowpass filtered by the circuit elements and the resulting output signalis nominally zero (zero dc value) with some ac ripple due to imperfectsuppression of the high frequency contents from the loop filter. Oncefrequency acquisition has been established, the phase error signal takesover and the frequency error feedback path is broken, indicatedsymbolically in the circuit of FIG. 4 by switch 102.

What has been added to the circuitry of FIG. 4 is the addition of abroadband lowpass filter 104 coupled to the output of multiplexer 84.The output of filter 104 has a frequency one-quarter the frequency ofthe bit rate. The output of filter 104 is then provided as inputs totrack and hold circuits 106 and 108. The output of circuits 106 and 108,in turn, are coupled to the inputs of multiplexer 110, whose outputagain is coupled to a lowpass filter 112. The output of filter 112 isdifferenced at summing node 114 with the phase error. The output fromnode 114 is then coupled through limiter 116 and provided to theswitched locked detect gate 102. The output of filter 104, whichrepresents the phase error, is also coupled to the input of a phasefilter 58b. The output of frequency filter 58a and phase filter 58b arethen summed at summing node 118 and provided to the input of VCO 61. Theremaining elements of the circuit of FIG. 3 are identical orsubstantially similar to similarly numbered elements shown and describedin connection with FIG. 3.

Many alterations and modifications may be made by those having ordinaryskill in the art without departing from the spirit and scope of theinvention. Therefore, it must be understood that the illustratedembodiment has been set forth only for the purposes of example and thatit should not be taken as limiting the invention as defined by thefollowing claims. The following claims are, therefore, to be read toinclude not only the combination of elements which are literally setforth, but all equivalent elements for performing substantially the samefunction in substantially the same way to obtain substantially the sameresult. The claims are thus to be understood to include what isspecifically illustrated and described above, what is conceptionallyequivalent, and also what essentially incorporates the essential idea ofthe invention.

I claim:
 1. A clock recovery circuit for establishing bitsynchronization with an NRZ data formatted bit stream comprising:amatched filter for receiving said NRZ data formatted bit stream forproducing a filtered output signal indicative of edge transitions insaid NRZ data formatted bit stream; first and second sample and holdcircuits having inputs coupled to said matched filter, said sample andhold circuits being complementarily clocked by a VCO signal to holdquadrature samples, said first sample and hold circuit for generating anin-phase data output signal; a third sample and hold circuit having aninput coupled to said second sample and hold circuit, said third sampleand hold circuit being clocked on positive and negative transitions ofsaid in-phase data output signal and generating a data crossover sample;a multiplier for multiplying said in-phase data output signal withoutput from said third sample and hold circuit; a lowpass filter coupledto said multiplier for filtering output of said multiplier to generate aDC value of a phase error signal proportional to any phase error betweensaid in-phase data output signal and said data crossover sample; and avariable controlled oscillator (VCO) having its control input coupled tosaid low ass filter, said variable controlled oscillator generating saidVCO signal with a controllable phase according to said DC value providedby said lowpass filter, said VCO being coupled to said first and secondsample and hold circuits to complementarily clock said first and secondsample and hold circuits, whereby a data transition tracking loop isprovided which is high speed, inherently self-adjusting: is independentof data transition density with significantly reduced ripple in saidphase error signal generated by said multiplier.
 2. The circuit of claim1 further comprising a first limiter coupled to the output of said firstsample and hold circuit, said first limiter having an output coupled tosaid multiplier so that output of said multiplier representative of saidphase error is monotonic across said phase error signal centered on abit interval, said output of said limiter being said in-phase dataoutput signal.
 3. The circuit of claim 2 wherein said phase error signaloutput by said multiplier is a sawtooth wave form.
 4. The circuit ofclaim 1 further comprising a limiter coupled to said VCO signal of saidVCO for generating a clock signal indicative of a recaptured clock fromsaid NRZ data formatted bit stream.
 5. The circuit of claim 2 furthercomprising a second limiter coupled to said VCO signal of said VCO forgenerating a clock signal indicative of a recaptured clock from said NRZdata formatted bit stream.
 6. The circuit of claim 2 further comprisinga frequency lock detector for providing a frequency error signal to saidVCO, said VCO being responsive to said frequency error signal to shiftfrequency of said VCO in alignment with bit rate frequency of said NRAdata formatted bit stream prior to phase lock.
 7. The circuit of claim 6wherein said frequency lock detector is enabled only when absolute valueof phase error exceeds a predetermined threshold.
 8. The circuit ofclaim 3 further comprising a frequency lock detector for providing afrequency error signal to said VCO, said VCO being responsive to saidfrequency error signal to shift frequency of said VCO in alignment withbit rate frequency of said NRZ data formatted bit stream prior to phaselock.
 9. The circuit of claim 1 arranged and configured to operate in abit interleaved fashion so that said first and second sample and holdcircuits each constitute a pair of complementarily clocked tracking andhold circuits having their input coupled to said matched filter and amultiplexer having its inputs coupled to outputs of said pair oftracking and hold circuits, said tracking and hold circuits beingcomplementarily clocked by selected outputs from said VCO, said VCOhaving a lead output, Q, and an lag output, I, said tracking and holdcircuits of said first sample and hold circuit being clocked by said lagoutput from said VCO while said pair of tracking and hold circuits ofsaid second sample and hold circuit are clocked by said lead output fromsaid VCO.
 10. The circuit of claim 9 wherein said third sample and holdcircuit constitutes:a pair of complementarily clocked tracking and holdcircuits complementarily clocked by said in-phase data output signal andhaving their input coupled to an output of said multiplexer includedwithin said second sample and hold circuit which generates datacross-over samples; a multiplexer coupled to outputs from said pair oftracking and hold circuits included in said third sample and holdcircuit, said multiplexer of said third sample and hold circuit havingan output coupled to said lowpass filter; and an inverter coupledbetween an output of one of said tracking and hold circuits and an inputof said multiplexer to invert tracked and held data crossover sampleswhen said tracking and hold circuit coupled thereto is clocked by anegative transition of said data output signal.
 11. The circuit of claim10 wherein said tracking and hold circuits and multiplexers comprisingsaid first, second and third sample and hold circuits are matchedthrough substantially identical integrated circuit fabrication toinherently null out systematic phase errors within each of said sampleand hold circuits.
 12. The circuit of claim 11 further comprising afrequency lock detector for providing a frequency error signal to saidVCO, said VCO being responsive to said frequency error signal to shiftfrequency of said VCO in alignment with bit rate frequency of said NRZdata formatted bit stream prior to phase lock.
 13. The circuit of claim12 wherein said frequency lock detector comprises a fourth sample andhold circuit comprised of:a pair of tracking and hold circuitscomplementarily clocked by said inphase data output signal each havingtheir inputs coupled to said lowpass filter; a multiplexer having itsinputs coupled to outputs of said pair of tracking and hold circuits ofsaid fourth sample and hold circuit; a second lowpass filter having itsinput coupled to an output of said multiplexer of said fourth sample andhold circuit; a summing node coupled to said second lowpass filter fordifferencing with said phase error signal; and a limiter having itsinput coupled to said summing node to generate a frequency error signal.14. The circuit of claim 13 further comprising a lock detect gate forbreaking connection between said limiter and said lowpass filter whenabsolute value of said phase error signal is below a predeterminedthreshold, so that said VCO is controlled only by said phase error belowsaid threshold and by said frequency error above said threshold.
 15. Amethod of recovering a clock signal from an NRZ data bit streamcomprising the steps of:detecting edge transitions of said NRZ data bitstream; generating a quadrature sample signal corresponding to said NRZdata bit stream; selectively passing said quadrature sample signal to aphase detector output, said quadrature sample signal being passed tosaid phase detector output if said NRZ data makes a low to hightransition, a negative of said quadrature sample signal being passed tosaid phase detector output if said NRZ data signal makes a high to lowtransition, otherwise if said NRZ data signal makes no transition,holding a previous phase error value in said phase detector output;controlling a variably controlled oscillator (VCO) according to saidphase detector output; and generating a recaptured clock signal by saidcontrolled VCO, whereby said clock signal is recovered in aself-adjusting circuit with no steady state phase error, whereby rippleinduced phase jitter is substantially eliminated, whereby phase erroroutput is independent of data density and high speed operation isenabled.
 16. The method of claim 15 further comprising the step ofgenerating from said output of said phase error detector a frequencyerror signal, said frequency error signal being selectively combinedwith output of said phase detector to control frequency of said VCO tothereby frequency lock to said NRZ data bit stream.
 17. The method ofclaim 15 further comprising the step of generating a monotonicallyincreasing phase error signal extending across a bit interval centeredon zero phase error for controlling said VCO.
 18. The method of claim 17wherein the step of generating said monotonically increasing phase errorsignal generates a sawtooth wave form.
 19. The method of claim 18wherein said frequency error signal is generated from said sawtooth waveform and further comprising the step of generating from said output ofsaid phase error detector a frequency error signal, said frequency errorsignal being selectively combined with output of said phase detector tocontrol frequency of said VCO to thereby frequency lock to said NRZ databit stream.
 20. A circuit for recapturing a clock signal from an NRZdata bit stream comprising:clocked sample and hold circuit means forsampling and holding an in-phase sample signal of said NRZ data bitstream; clocked sample and hold circuit means for sampling and holding-aquadrature sample signal of said NRZ data bit stream; phase detectorcircuit means for selectively passing said quadrature sample signal to aphase detector output, said quadrature sample signal being passed tosaid phase detector output if said NRZ data makes a low to hightransition, the negative of said quadrature sample signal being passedto said phase detector output if said NRZ data makes a high to lowtransition, and previously passed quadrature sample signal being held atsaid phase detector output if said NRZ data makes no transition; andvariable controlled oscillator means for receiving said phase detectoroutput and responsively generating an in-phase clock signal, saidclocked sample and hold circuit means for sampling and holding anin-phase sample signal of said NRZ data bit stream and said clockedsample and hold circuit means for sampling and holding a quadraturesample signal of said NRZ data bit stream being complementarily clockedby said inphase clock signal.